Conventionally, voltage conversion devices that drive switching elements with a PWM signal to convert a voltage are widely used. In such voltage conversion devices of a PWM control type, for example, a voltage command value is calculated based on a target voltage value, values that correspond to the calculated voltage command value are set in PWM signal generating units, and thereby PWM signals having duty cycles that correspond to the setting values are generated. By changing the duty cycles of the PWM signals that drive the switching elements based on the target voltage value in this way, an output voltage that corresponds to the target voltage value can be obtained.
Here, if the values that are settable in the PWM signal generating units (hereinafter, referred to as “settable values”) have a relatively large minimum unit (that is, minimum increment), the duty cycles of the PWM signals cannot smoothly be changed in response to a change in the target value, and the output voltage will change stepwise. Furthermore, for example, if target values that are to be set in the PWM signal generating units are calculated as operation amounts in PWM control, and a minimum unit of the settable values is larger than a minimum unit of the target values, the duty cycles of the PWM signals cannot smoothly be changed in response to a change in the target voltage value and a load change, and an error will occur in the output voltage.
To solve this, JP-H03-98470A discloses a PWM inverter that calculates an on/off time of a PWM signal in each period of PWM control using the division such that a voltage command value is used as a dividend and a remainder is truncated, and outputs a PWM pulse based on the calculation result. The remainder obtained in the above-described calculation corresponds to a voltage command value that is truncated without being reflected in the on/off time.
In this PWM inverter, the truncated remainders are sequentially added to voltage command values in the calculation in the next period onwards, such that a remainder that was not reflected in an on/off time in the previous calculation is reflected in a new on/off time in the next calculation, and a remainder that is obtained in this calculation is reflected in the calculation after the next calculation, and such processes are repeated. Accordingly, it is possible to bring an average on/off time that is to be set in the PWM signal generating units close to a target on/off time that is set ideally. In other words, it is possible to make a minimum unit of values that are to be set in generating units on average smaller than an actual minimum unit.
However, in the technique disclosed in JP-H03-98470A, calculation including division is executed in each period of PWM control to determine an on/off time of a PWM signal, and thus a high processing load occurs in each period. Accordingly, there is a risk that an inexpensive microcomputer having low throughput cannot complete the above-described calculation processing within one period of PWM control. Furthermore, JP-H03-98470A does not take into consideration application of the inventive technique to a plurality of inverters.
The present invention was made in view of such circumstances, and it is an object of thereof to provide a signal generating circuit, a voltage conversion device, and a signal generating method in which it is possible to make a minimum unit of values that are respectively set in m (where m is a natural number equal to or greater than 2) generating units that periodically generate PWM signals corresponding to the setting values substantially smaller than an actual minimum unit.